Tools I Use as a Designer
Over 14 years of analog, mixed-signal and RF layout I have worked with many tool flows across different foundries and companies. These are the tools I rely on most, and how each one fits into the work.
Layout design tools
- Cadence Virtuoso (IC5 through IC12.3 and ICADV): my main environment for full-custom layout, from device placement to full-chip assembly.
- Synopsys Custom Compiler: used on programs whose flow is built around Synopsys.
- Tanner L-Edit: useful for smaller and mature-node projects.
Physical verification tools
- Siemens Calibre: the industry reference for DRC, LVS and PERC; most of my sign-off work runs through it.
- Cadence Assura and Pegasus (PVS) and Synopsys ICV: used where the foundry or customer flow requires them.
Whatever the tool, clean verification depends on understanding the rule deck. During my time leading Extraction and PERC PDK QA at Intel, I saw how much design quality depends on PDK quality.
Automation: Cadence SKILL and Python
Layout has many repetitive tasks: generating arrays, placing guard rings, checking naming, collecting verification results. I use Cadence SKILL inside Virtuoso and Python for data handling and reporting to automate them. Good automation frees engineers to spend time on the decisions that affect performance.
AI-assisted workflows
AI-assisted tools are starting to help with routine layout steps, script writing and review. I treat them as an assistant: they speed things up, but every result still goes through the same verification and engineering judgement.
Collaboration tools
On multi-site programs, data management tools such as IC Manage and ClioSoft, and remote environments such as Citrix, keep teams in different countries working on the same design safely.
Advice for new engineers
Learn one layout tool and one verification tool deeply before collecting many. Then learn a scripting language. Engineers who can automate their own work become valuable very quickly.
