Selected Projects
Most semiconductor work is confidential, so these projects are described by type rather than by customer. Each was taken through full physical verification to tape-out.
Together they cover more than 14 years of analog, mixed-signal, RF and memory layout, from 180nm down to 1.4nm.
Projects
From Transistor Level to Tape-Out
Full-Chip Designs
Scratch to GDS: LED driver, smart switch, analog front-end (AFE), medical ultrasound chip, power recharge chip, PMIC, and automotive and medical designs, with full LVS/DRC/ERC verification and ECOs for yield.
SerDes at 7nm and 8nm
High- and medium-speed SerDes from transistor level to chip top: floorplanning, multi-supply power delivery, APG buffer placement, density fixes, decaps and coaxial channel shielding.
Test Chips
Full-chip layout and post-layout verification across technologies: power distribution, bump and decap placement, antenna diodes, ESD and power clamps, and Rx/Tx blocks with symmetric routing.
Analog & RF Blocks
Bandgaps, LNAs, drivers, filters, op-amps, current bias circuits, mixers and RF transceivers on 14nm, 16nm and 22FD-SOI, with low-parasitic routing and BJT matching.
SRAM & OTP Memory
SRAM tag and data array macros on 28nm, 20nm and FinFET, and OTP modules from 8K to 128K delivered from floorplan to GDSII over 2+ years.
PDK Quality Assurance at Intel
Led the Extraction and PERC PDK QA teams: resolved layout issues found in QA, optimised IPs and created QA cells, with over 95% of projects on time.
Collaborate
Working on Something Similar?
I’m always happy to talk about analog layout challenges, speaking invitations or mentoring. Send me a message and I’ll get back to you.